The Book: Chip Multiprocessor Architecture

A summary of the highlights of my research is now available in the concise book Chip Multiprocessor Architecture, by Kunle Olukotun, myself, and James Laudon (Morgan & Claypool, December 2007). Several chapters are condensed and streamlined versions of text from several of the publications below.

A PDF version is available directly from Morgan & Claypool's Synthesis Lectures on Computer Architecture website.

Paper versions are available from many technical booksellers, including

A Guide:

I authored or co-authored all of the following publications during my years at Stanford. All of the following documents are downloadable in Adobe PDF format if you would like to read the entire article, report, or paper.

We start with publications describing general background information about my work.

The following papers describe Transactional Coherence and Consistency (TCC), a method for using speculation to eliminate conventional cache coherence and consistency models.

These describe computer architecture case studies we performed that led to the Hydra design.

The following papers offer views of low-level aspects of Hydra, including descriptions of the originally planned chip design and our later FPGA emulation environment.

My PhD dissertation includes most of the information in the "low-level" papers, organized into a logical sequence, plus a large amount of additional details on the Hydra hardware and software design.

The following papers deal with a variant of Hydra we explored using DRAM instead of SRAM as a basis for the large, on-chip secondary memory bank.

The Publications, in reverse chronological order:

Last Revised 7/21/08